S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 347

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Read: anytime
Write: anytime (any value written causes PWM counter to be reset to 0x0000).
10.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
Reference
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
Freescale Semiconductor
Module Base + 0x00011
Reset
•
•
•
•
•
•
W
R
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
Left aligned output (CAEx = 0)
PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1)
PWMx period = channel clock period * (2 * PWMPERx)
Section 10.4.2.3, “PWM Period and Duty,”
Bit 7
0
0
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 10-20. PWM Channel Counter Registers (PWMCNT5)
6
0
0
6
S12P-Family Reference Manual, Rev. 1.13
5
0
0
5
NOTE
4
0
0
4
for more information.
Section 10.4.2.8, “PWM Boundary Cases.”
Pulse-Width Modulator (PWM8B6CV1) Block Description
3
0
0
3
2
0
0
2
1
0
0
1
Bit 0
0
0
0
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