S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 466

• Manufacturer Part Number: S9S12P64J0CFTR
• Description: 16-bit Microcontrollers - MCU 16-bit 64K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P64J0CFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.15 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

128 KByte Flash Module (S12FTMRC128K1V1)
13.4.5.14 Erase Verify D-Flash Section Command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased. The
Erase Verify D-Flash Section command defines the starting point of the data to be verified and the number
of words.
466
Register
FSTAT
Field margin levels must only be used during verify of the initial factory
programming.
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
MGSTAT1
MGSTAT0
Table 13-58. Set Field Margin Level Command Error Handling
ACCERR
Error Bit
FPVIOL
1. Read margin to the erased state
2. Read margin to the programmed state
(CCOBIX=001)
Table 13-57. Valid Set Field Margin Level Settings
0x0000
0x0001
0x0002
0x0003
0x0004
CCOB
S12P-Family Reference Manual, Rev. 1.13
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see
Set if an invalid global address [17:16] is supplied
Set if an invalid margin level setting is supplied
None
None
None
CAUTION
NOTE
Return to Normal Level
User Margin-1 Level
User Margin-0 Level
Field Margin-1 Level
Field Margin-0 Level
Level Description
Error Condition
(1)
(2)
1
2
Table
13-27)
Freescale Semiconductor