S9S12P64J0CFTR Freescale Semiconductor, S9S12P64J0CFTR Datasheet - Page 311
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S9S12P64J0CFTR
Manufacturer Part Number
S9S12P64J0CFTR
Description
16-bit Microcontrollers - MCU 16-bit 64K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P64J0CFTR
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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9.3.2.2
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0001
ETRIGSEL
SRES[1:0]
Reset
Field
6–5
W
7
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-
0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in
A/D Resolution Select — These bits select the resolution of A/D conversion results. See
WRAP3 WRAP2 WRAP1 WRAP0
1. If only AN0 should be converted use MULT=0.
0
0
1
1
1
1
1
1
1
1
SRES1
0
6
1
1
0
0
0
0
1
1
1
1
Table 9-2. Multi-Channel Wrap Around Coding
Figure 9-4. ATD Control Register 1 (ATDCTL1)
Table 9-3. ATDCTL1 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
SRES0
1
1
0
0
1
1
0
0
1
1
1
5
0
1
0
1
0
1
0
1
0
1
SMP_DIS
0
4
Multiple Channel Conversions (MULT = 1)
Table
Wraparound to AN0 after Converting
Description
9-5.
ETRIGCH3
1
3
AN6
AN7
AN8
AN9
AN9
AN9
AN9
AN9
AN9
AN9
ETRIGCH2
Analog-to-Digital Converter (ADC12B10C)
1
2
ETRIGCH1
1
1
Table 9-4
ETRIGCH0
for coding.
1
0
311
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