TMPSNS-RTD1 Microchip Technology, TMPSNS-RTD1 Datasheet - Page 323

• Manufacturer Part Number: TMPSNS-RTD1
• Description: BOARD EVAL PT100 RTD TEMP SENSOR
• Manufacturer: Microchip Technology

Specifications of TMPSNS-RTD1

• Sensor Type: Temperature
• Interface: USB
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: MCP3301, MCP6S26, PIC18F2550
• Processor To Be Evaluated: MCP6S26, MCP3301, MCP6024, MCP41010, PIC18F2550, TC1071, MCP6002
• Data Bus Width: 12 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Voltage - Supply: -
• Sensitivity: -
• Sensing Range: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
ANDWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .AND. (f) → dest
N, Z
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ANDWF
Read
0001
Q2
17h
C2h
02h
C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
ffff
destination
Write to
PIC18F2455/2550/4455/4550
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
BC
-128 ≤ n ≤ 127
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
None
If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
0010
operation
BC
Process
Process
Data
Data
No
Q3
Q3
DS39632E-page 321
5
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn