TMPSNS-RTD1 Microchip Technology, TMPSNS-RTD1 Datasheet - Page 324
TMPSNS-RTD1
Manufacturer Part Number
TMPSNS-RTD1
Description
BOARD EVAL PT100 RTD TEMP SENSOR
Manufacturer
Microchip Technology
Datasheets
1.MCP3301-CIMS.pdf
(32 pages)
2.PCM18XR1.pdf
(438 pages)
3.MCP6S22DM-PICTL.pdf
(43 pages)
4.TMPSNS-RTD1.pdf
(26 pages)
Specifications of TMPSNS-RTD1
Sensor Type
Temperature
Interface
USB
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
MCP3301, MCP6S26, PIC18F2550
Processor To Be Evaluated
MCP6S26, MCP3301, MCP6024, MCP41010, PIC18F2550, TC1071, MCP6002
Data Bus Width
12 bit
Interface Type
USB
Lead Free Status / RoHS Status
Not applicable / Not applicable
Voltage - Supply
-
Sensitivity
-
Sensing Range
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable
- MCP3301-CIMS PDF datasheet
- PCM18XR1 PDF datasheet #2
- MCP6S22DM-PICTL PDF datasheet #3
- TMPSNS-RTD1 PDF datasheet #4
- Current page: 324 of 438
- Download datasheet (7Mb)
PIC18F2455/2550/4455/4550
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39632E-page 322
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG =
FLAG_REG =
Q1
register ‘f’
Bit Clear f
BCF
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
0 → f<b>
None
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
BCF
Read
1001
Q2
f, b {,a}
C7h
47h
FLAG_REG,
bbba
Process
Data
Q3
ffff
7, 0
register ‘f’
Write
Q4
ffff
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Negative
If Negative
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
BN
-128 ≤ n ≤ 127
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
None
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
‘n’
‘n’
Q2
Q2
=
=
=
=
=
© 2009 Microchip Technology Inc.
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
0110
operation
BN
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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