DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 33

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
Transceivers
Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D, EP1AGX50D, and EP1AGX60D
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E
© December 2009 Altera Corporation
Region0 8 LRIO clock
Region1 8 LRIO clock
Region0 8 LRIO clock
Region1 8 LRIO clock
Region2 8 LRIO clock
Region3 8 LRIO clock
Source
Source
Figure 2–24. Regional Clock Resources in Arria GX Devices
For the RCLK or GCLK network to route into the transceiver, a local route input
output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths
and each transceiver block has a maximum of eight clock paths for connecting with
LRIO clocks. These resources are limited and determine the number of clocks that can
be used between the PLD and transceiver blocks.
number of LRIO resources available for Arria GX devices with different numbers of
transceiver blocks.
Global Clock
Global Clock
v
v
v
v
v
v
CLK[3..0]
Clock Resource
Clock Resource
7
1
2
8
Regional Clock
Regional Clock
RCLK 20-27
RCLK 12-19
RCLK 20-27
RCLK 20-27
RCLK 12-19
RCLK 12-19
RCLK
RCLK
[3..0]
[7..4]
[31..28]
RCLK
RCLK
[11..8]
CLK[15..12]
8 Clock I/O
CLK[7..4]
11 5
12 6
Bank13
8 Clock I/O
v
v
—
—
Bank13
v
—
[27..24]
[15..12]
RCLK
RCLK
Table 2–7
Transceiver
Transceiver
8 Clock I/O
Bank14
[23..20]
[19..16]
RCLK
RCLK
v
v
—
—
Arria GX Device Handbook, Volume 1
and
8 Clock I/O
Bank14
Table 2–8
v
Transceiver
Transceiver
—
Arria GX
Arria GX
Block
Block
8 Clock I/O
Bank15
v
v
—
—
list the
2–27