DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 75

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–56. Dual-Regional Clocks
Figure 2–57. Hierarchical Clock Networks Per Quadrant
© December 2009 Altera Corporation
PLLs
CLK[3..0]
Regional Clock Network [7..0]
Global Clock Network [15..0]
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources consisting of
16 global clock lines and eight regional clock lines. Multiplexers are used with these
clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select three of the six row clocks to
feed the ALM registers in the LAB (refer to
You can use the Quartus II software to control whether a clock input pin drives either
a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects
the clocking resources if not specified.
CLK[7..4]
CLK[15..12]
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [23..0]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
PLLs
CLK[3..0]
Figure
2–57).
CLK[7..4]
Arria GX Device Handbook, Volume 1
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
CLK[15..12]
2–69