DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 81

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs
Note to
(1) The GCLK or RCLK in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 2)
© December 2009 Altera Corporation
Clock Pins
CLK0p
CLK1p
CLK2p
CLK3p
Drivers from Internal Logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
Clock Network Connectivity
Left Side Global & Regional
source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure
2–63:
PLL 7
PLL 8
Fast
Fast
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
C0
C1
C2
C3
C0
C1
C2
C3
v
v
—
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v
v
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—
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—
RCLK0
RCLK4
v
v
v
v
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—
RCLK1
RCLK5
RCLK2
RCLK6
v
v
v
v
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—
RCLK3
RCLK7
v
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v
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v
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GCLK0
v
v
v
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GCLK1
v
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v
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GCLK2
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v
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v
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GCLK3
v
v
v
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Arria GX Device Handbook, Volume 1
v
v
v
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(Note 1)
v
v
v
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v
v
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