DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 57

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–43. M512 RAM Block LAB Row Interface
M4K RAM Blocks
© December 2009 Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block
is used to implement buffers for a wide variety of applications such as storing
processor code, implementing lookup schemes, and implementing larger memory
applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM
blocks can be configured in the following modes:
■
■
■
■
■
■
When configured as RAM or ROM, you can use an initialization file to pre-load the
memory contents.
M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the
two clocks feeding the block can clock M4K RAM block registers (renwe, address,
byte enable, datain, and output registers). Only the output register can be
bypassed. The six labclk signals or local interconnects can drive the control signals
for the A and B ports of the M4K RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b
signals, as shown in
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
M4K RAM Block Local
Interconnect Region
16
Figure
datain
control
signals
clocks
2–44.
LAB Row Clocks
M4K RAM
address
Block
dataout
byte
enable
36
6
Arria GX Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
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