DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 73

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–54. Global Clocking
© December 2009 Altera Corporation
Regional Clock Network
There are eight RCLK networks (RCLK[7..0]) in each quadrant of the Arria GX
device that are driven by the dedicated CLK[15..12]and CLK[7..0] input pins, by
PLL outputs, or by internal logic. The regional clock networks provide the lowest
clock delay and skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as shown in
Figure
CLK[3..0]
2–55.
Global Clock [15..0]
CLK[7..4]
CLK[15..12]
Global Clock [15..0]
Arria GX Device Handbook, Volume 1
2–67