DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 72

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–66
PLLs and Clock Networks
Global and Hierarchical Clocking
Table 2–16. Global and Regional Clock Features
Arria GX Device Handbook, Volume 1
Number per device
Number available per
quadrant
Sources
Dynamic clock source
selection
Dynamic enable/disable
Feature
Arria GX devices provide a hierarchical clock structure and multiple PLLs with
advanced features. The large number of clocking resources in combination with the
clock synthesis precision provided by enhanced and fast PLLs provides a complete
clock management solution.
Arria GX devices provide 16 dedicated global clock networks and 32 regional clock
networks (eight per device quadrant). These clocks are organized into a hierarchical
clock structure that allows for up to 24 clocks per device region with low skew and
delay. This hierarchical clocking scheme provides up to 48 unique clock domains in
Arria GX devices.
There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to drive either the
global or regional clock networks. Four clock pins drive each side of the device except
the right side, as shown in
and fast PLL outputs can also drive the global and regional clock networks. Each
global and regional clock has a clock control block, which controls the selection of the
clock source and dynamically enables or disables the clock to reduce power
consumption.
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. GCLK
networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP
blocks, and all memory blocks. These resources can also be used for control signals,
such as clock enables and synchronous or asynchronous clears fed from the external
pin. The global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other control
signals with large fanout.
clock networks.
Clock pins, PLL outputs, core routings,
inter-transceiver clocks
Table 2–16
Global Clocks
lists the global and regional clock features.
16
v
v
16
Figure 2–54
Figure 2–54
shows the 12 dedicated CLK pins driving global
and
Figure
Clock pins, PLL outputs, core routings,
inter-transceiver clocks
2–55. Internal logic and enhanced
© December 2009 Altera Corporation
Regional Clocks
Chapter 2: Arria GX Architecture
32
—
v
8
PLLs and Clock Networks