DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 63

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–49. M-RAM Row Unit Interface to Interconnect
© December 2009 Altera Corporation
Direct Link
Interconnects
Table 2–12
and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals (Part 1 of 2)
Unit Interface Block
LAB
lists the input and output data signal connections along with the address
L0
L1
L2
L3
C4 Interconnect
M-RAM Block to
LAB Row Interface
Block Interconnect Region
16
datain_a[14..0]
byteena_a[1..0]
datain_a[29..15]
byteena_a[3..2]
datain_a[35..30]
addressa[4..0]
addr_ena_a
clock_a
clocken_a
renwe_a
aclr_a
addressa[15..5]
datain_a[41..36]
Row Interface Block
R4 and R24 Interconnects
Input Signals
Up to 16
Up to 28
M-RAM Block
dataout_a[ ]
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteena
clocken_a
clock_a
aclr_a
dataout_a[11..0]
dataout_a[23..12]
dataout_a[35..24]
dataout_a[47..36]
A
Arria GX Device Handbook, Volume 1
[ ]
Output Signals
2–57