DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 51

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–39. R4 Interconnect Connections
Notes to
(1) C4 and C16 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
(3) The LABs in
© December 2009 Altera Corporation
Figure
2–39:
Figure 2–39
R24 row interconnects span 24 LABs and provide the fastest resource for long row
connections between LABs, TriMatrix memory, DSP blocks, and row IOEs. The R24
row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row
or column interconnects at every fourth LAB and do not drive directly to LAB local
interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4
interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The
column interconnect operates similarly to the row interconnect and vertically routes
signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of
LABs is served by a dedicated column interconnect.
These column resources include:
■
■
■
■
■
Arria GX devices include an enhanced interconnect structure in LABs for routing
shared arithmetic chains and carry chains for efficient arithmetic functions. The
register chain connection allows the register output of one ALM to connect directly to
the register input of the next ALM in the LAB for fast shift registers. These
ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization and
performance.
chain interconnects.
show the 16 possible logical outputs per LAB.
Shared arithmetic chain interconnects in a LAB
Carry chain interconnects in a LAB and from LAB to LAB
Register chain interconnects in a LAB
C4 interconnects traversing a distance of four blocks in up and down direction
C16 column interconnects for high-speed vertical routing through the device
R4 Interconnect
Driving Left
Figure 2–40
(Note
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
Neighbor
LAB
1), (2),
shows shared arithmetic chain, carry chain, and register
(3)
Primary
LAB (2)
C4 and C16
Column Interconnects (1)
Neighbor
LAB
R4 Interconnect
Driving Right
Arria GX Device Handbook, Volume 1
2–45