ST92E163-EPB/US STMicroelectronics, ST92E163-EPB/US Datasheet - Page 46
ST92E163-EPB/US
Manufacturer Part Number
ST92E163-EPB/US
Description
KIT DEMO MASS STORAGE
Manufacturer
STMicroelectronics
Type
Microcontroller Programmerr
Datasheet
1.ST92E163-EPBUS.pdf
(230 pages)
Specifications of ST92E163-EPB/US
Contents
Programmer, Cable, Power Supply, Software, Manual and more
For Use With/related Products
ST9 MCUs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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ST92163R4 - INTERRUPTS
3 INTERRUPTS
3.1 INTRODUCTION
The ST9 responds to peripheral and external
events through its interrupt channels. Current pro-
gram execution can be suspended to allow the
ST9 to execute a specific response routine when
such an event occurs, providing that interrupts
have been enabled, and according to a priority
mechanism. If an event generates a valid interrupt
request, the current program status is saved and
control passes to the appropriate Interrupt Service
Routine.
The ST9 CPU can receive requests from the fol-
lowing sources:
– On-chip peripherals
– External pins
– Top-Level Pseudo-non-maskable interrupt
According to the on-chip peripheral features, an
event occurrence can generate an Interrupt re-
quest which depends on the selected mode.
Up to eight external interrupt channels, with pro-
grammable input trigger edge, are available. In ad-
dition, a dedicated interrupt channel, set to the
Top-level priority, can be devoted either to the ex-
ternal NMI pin (where available) to provide a Non-
Maskable Interrupt, or to the Timer/Watchdog. In-
46/230
terrupt service routines are addressed through a
vector table mapped in Memory.
Figure 19. Interrupt Response
INTERRUPT
PROGRAM
NORMAL
FLOW
INSTRUCTION
PENDING BIT
INTERRUPT
ROUTINE
SERVICE
CLEAR
IRET
VR001833
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