ST92E163-EPB/US STMicroelectronics, ST92E163-EPB/US Datasheet - Page 54

• Manufacturer Part Number: ST92E163-EPB/US
• Description: KIT DEMO MASS STORAGE
• Manufacturer: STMicroelectronics
• Type: Microcontroller Programmerr

Specifications of ST92E163-EPB/US

• Contents: Programmer, Cable, Power Supply, Software, Manual and more
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST92163R4 - INTERRUPTS
3.6 EXTERNAL INTERRUPTS
The standard ST9 core contains 8 external inter-
rupts sources grouped into four pairs.
INT7 is connected to 8 different I/O pins of Port 3.
Once these pins are programmed as alternate
function they are able to generate an interrupt.
Table 11. External Interrupt Channel Grouping
INT0 .. 6 have a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243, EIPR.0,..,6 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
through
IMA0,..,IMD1 (EIMR.6,..,0). See
INT7 is falling edge sensitive only, bit EIMR.7 must
always be cleared.
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2, PRL1. For each pair, the even
channel (A0,B0,C0,D0) of the group has the even
priority level and the odd channel (A1,B1,C1,D1)
has the odd (lower) priority level.
54/230
External Interrupt
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
the
corresponding
Figure
Channel
INTD1
INTD0
INTC1
INTC0
INTB1
INTB0
INTA1
INTA0
control
27.
bit
Figure 26. Priority Level Examples
n
Figure 26
Figure 27
rupt control bits and vectors.
– The source of the interrupt channel A0 can be
– The source of the interrupt channel A1 can be
– The source of the interrupt channel D0 can be
Important: When using channels shared by both
external interrupts and peripherals, special care
must be taken to configure their control registers
for both peripherals and interrupts.
Table 12. Multiplexed Interrupt Sources
INT.D0:
INT.D1:
INT.C1: 001=1
SOURCE
INT.C0: 000=0
Channel
selected between the external pin INT0 (when
IA0S = “1”, the reset value) or the On-chip Timer/
Watchdog peripheral (when IA0S = “0”).
selected between the external pin INT1 (when
AD-INT=“0”) or the on-chip ADC peripheral
(when AD-INT=“1”, the reset value).
selected between the external pin INT6 (when
INT_SEL = “0”) or the on-chip RCCU.
INTD0
INTA0
INTA1
101=5
100=4
PRIORITY
shows an example of priority levels.
gives an overview of the External inter-
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
Internal Interrupt
1
Timer/Watchdog
0
Source
RCCU
ADC
0
0
1
0
External Interrupt
0
1
SOURCE
Source
INT.A0: 010=2
INT.A1: 011=3
INT.B0: 100=4
INT.B1: 101=5
INT0
INT1
INT6
EIPLR
VR000151
PRIORITY