ST92E163-EPB/US STMicroelectronics, ST92E163-EPB/US Datasheet - Page 58

• Manufacturer Part Number: ST92E163-EPB/US
• Description: KIT DEMO MASS STORAGE
• Manufacturer: STMicroelectronics
• Type: Microcontroller Programmerr

Specifications of ST92E163-EPB/US

• Contents: Programmer, Cable, Power Supply, Software, Manual and more
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST92163R4 - INTERRUPTS
3.10 INTERRUPT RESPONSE TIME
The interrupt arbitration protocol functions com-
pletely asynchronously from instruction flow, and
requires 6 CPUCLK cycles to resolve the request’s
priority.
Requests are sampled every 5 CPUCLK cycles.
If the interrupt request comes from an external pin,
the trigger event must occur a minimum of one
INTCLK cycle before the sampling time.
When an arbitration results in an interrupt request
being generated, the interrupt logic checks if the
current instruction (which could be at any stage of
execution) can be safely aborted; if this is the
case, instruction execution is terminated immedi-
ately and the interrupt request is serviced; if not,
the CPU waits until the current instruction is termi-
nated and then services the request. Instruction
execution can normally be aborted provided no
write operation has been performed.
For an interrupt deriving from an external interrupt
channel, the response time between a user event
and the start of the interrupt service routine can
range from a minimum of 26 clock cycles to a max-
imum of 48 clock cycles.
58/230
For a non-maskable Top Level interrupt, the re-
sponse time between a user event and the start of
the interrupt service routine can range from a min-
imum of 22 clock cycles to a maximum of 48 clock
cycles.
In order to guarantee edge detection, input signals
must be kept low/high for a minimum of one
INTCLK cycle.
An interrupt machine cycle requires a basic 18 in-
ternal clock cycles (CPUCLK), to which must be
added a further 2 clock cycles if the stack is in the
Register File. 2 more clock cycles must further be
added if the CSR is pushed (ENCSR =1).
The interrupt machine cycle duration forms part of
the two examples of interrupt response time previ-
ously quoted; it includes the time required to push
values on the stack, as well as interrupt vector
handling.
In Wait for Interrupt mode, a further cycle is re-
quired as wake-up delay.