ST92E163-EPB/US STMicroelectronics, ST92E163-EPB/US Datasheet - Page 81
ST92E163-EPB/US
Manufacturer Part Number
ST92E163-EPB/US
Description
KIT DEMO MASS STORAGE
Manufacturer
STMicroelectronics
Type
Microcontroller Programmerr
Datasheet
1.ST92E163-EPBUS.pdf
(230 pages)
Specifications of ST92E163-EPB/US
Contents
Programmer, Cable, Power Supply, Software, Manual and more
For Use With/related Products
ST9 MCUs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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5.4 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
System Register
Reset Value: 1110 0000 (E0h)
*Note: This register contains bits which relate to
other functions; these are described in the chapter
dealing with Device Architecture. Only those bits
relating to Clock functions are described here.
Bit 5 = DIV2: OSCIN Divided by 2.
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
0: No division of the OSCIN Clock
1: OSCIN clock is internally divided by 2
Bit 4:2 = PRS[2:0]: Clock Prescaling.
These bits define the prescaler value used to pres-
cale CPUCLK from INTCLK. When these three
bits are reset, the CPUCLK is not prescaled, and is
equal to INTCLK; in all other cases, the internal
clock is prescaled by the value of these three bits
plus one.
7
-
-
DIV2
PRS2
PRS1
PRS0
ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU)
-
0
-
CLOCK CONTROL REGISTER (CLKCTL)
R240 - Read Write
Register Page: 55
Reset Value: 0000 0000 (00h)
Bit 7 = INT_SEL: Interrupt Selection.
0: Select the external interrupt pin as interrupt
1: Select the internal RCCU interrupt (see
Bit 6:4 = Reserved.
Must be kept reset for normal operation.
Bit 3 = SRESEN: Software Reset Enable.
0: The HALT instruction turns off the quartz, the
1: A Reset is generated when HALT is executed
Bit 2 = CKAF_SEL: Alternate Function Clock Se-
lect.
0: CK_AF clock not selected
1: Select CK_AF clock
Note: To check if the selection has actually oc-
curred, check that CKAF_ST is set. If no CK_AF
clock is present, the selection will not occur.
Bit 1 = WFI_CKSEL: WFI Clock Select.
This bit selects the clock used in Low power WFI
mode if LPOWFI = 1.
0: INTCLK during WFI is CLOCK2/16
1: INTCLK during WFI is CK_AF, providing it is
WARNING: When the CK_AF is selected as Low
Power WFI clock but the XTAL is not turned off
(R242.4 = 0), after exiting from the WFI, CK_AF
will be still selected as system clock. In this case,
reset the R240.2 bit to switch back to the XT.
Bit 0 = LPOWFI: Low Power mode during Wait For
0: Low Power mode during WFI disabled. When
1: The ST9 enters Low Power mode when the WFI
INT_S
EL
source (Reset state)
5.3.5)
PLL and the CCU
present. In effect this bit sets CKAF_SEL in WFI
mode
Interrupt.
WFI is executed, the CPUCLK is stopped and
INTCLK is unchanged
instruction is executed. The clock during this
state depends on WFI_CKSEL
7
-
-
-
SRE-
SEN
CKAF_S
EL
WFI_CKS
EL
Section
81/230
LPOW
FI
0
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