IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part NumberATMEGA48V-10MU
DescriptionIC AVR MCU 4K 10MHZ 1.8V 32-QFN
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48V-10MU datasheets
 


Specifications of ATMEGA48V-10MU

Core ProcessorAVRCore Size8-Bit
Speed10MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFNPackage32MLF EP
Device CoreAVRFamily NameATmega
Maximum Speed10 MHzOperating Supply Voltage2.5|3.3|5 V
Data Bus Width8 BitNumber Of Programmable I/os23
Interface TypeSPI/TWI/USARTOn-chip Adc8-chx10-bit
Number Of Timers3Processor SeriesATMEGA48x
CoreAVR8Data Ram Size512 B
Maximum Clock Frequency10 MHzMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Minimum Operating Temperature- 40 CController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed10MHz
No. Of Timers3Rohs CompliantYes
For Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 126/378

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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COM1x1:0 to three (See
page
130). The actual OC1x value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-
ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle
with a 50% duty cycle.
15.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
(clk
TCNTn
OCRnx
OCFnx
Figure 15-11
ATmega48/88/168
126
f
OCnxPFCPWM
Figure 15-10
clk
I/O
clk
Tn
/1)
I/O
OCRnx - 1
shows the same timing data, but with the prescaler enabled.
f
clk_I/O
=
--------------------------- -
2 N TOP
) is therefore shown as a
T1
shows a timing diagram for the setting of OCF1x.
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
Table on
2545S–AVR–07/10