IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part NumberATMEGA48V-10MU
DescriptionIC AVR MCU 4K 10MHZ 1.8V 32-QFN
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48V-10MU datasheets
 


Specifications of ATMEGA48V-10MU

Core ProcessorAVRCore Size8-Bit
Speed10MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFNPackage32MLF EP
Device CoreAVRFamily NameATmega
Maximum Speed10 MHzOperating Supply Voltage2.5|3.3|5 V
Data Bus Width8 BitNumber Of Programmable I/os23
Interface TypeSPI/TWI/USARTOn-chip Adc8-chx10-bit
Number Of Timers3Processor SeriesATMEGA48x
CoreAVR8Data Ram Size512 B
Maximum Clock Frequency10 MHzMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Minimum Operating Temperature- 40 CController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed10MHz
No. Of Timers3Rohs CompliantYes
For Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 283/378

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ATmega48/88/168
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega48/88/168 and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SELFPRGEN will be cleared).
Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section cannot be
re-enabled while the Flash is busy with a Page Erase or a Page Write (SELFPRGEN is set). If
the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort
and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in
R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared
upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See
“Reading the Fuse and Lock Bits from Software” on page 276
for
details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW
section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-
ing the entire Page Write operation if the NRWW section is addressed.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an
SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SELFPRGEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
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