IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part NumberATMEGA48V-10MU
DescriptionIC AVR MCU 4K 10MHZ 1.8V 32-QFN
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48V-10MU datasheets
 


Specifications of ATMEGA48V-10MU

Core ProcessorAVRCore Size8-Bit
Speed10MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFNPackage32MLF EP
Device CoreAVRFamily NameATmega
Maximum Speed10 MHzOperating Supply Voltage2.5|3.3|5 V
Data Bus Width8 BitNumber Of Programmable I/os23
Interface TypeSPI/TWI/USARTOn-chip Adc8-chx10-bit
Number Of Timers3Processor SeriesATMEGA48x
CoreAVR8Data Ram Size512 B
Maximum Clock Frequency10 MHzMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Minimum Operating Temperature- 40 CController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed10MHz
No. Of Timers3Rohs CompliantYes
For Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 298/378

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27.8.1
Serial Programming Pin Mapping
Table 27-15. Pin Mapping Serial Programming
Symbol
27.8.2
Serial Programming Algorithm
When writing serial data to the ATmega48/88/168, data is clocked on the rising edge of SCK.
When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See
Figure 27-9
To program and verify the ATmega48/88/168 in the serial programming mode, the following
sequence is recommended (See Serial Programming Instruction set in
299):
1. Power-up sequence:
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchro-
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of
the address. If polling (RDY/BSY) is not used, the user must wait at least t
issuing the next page (See
before the Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY) is not used, the
user must wait at least t
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is
not used, the used must wait at least t
27-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
ATmega48/88/168
298
Pins
MOSI
PB3
MISO
PB4
SCK
PB5
for timing details.
and GND while RESET and SCK are set to “0”. In some sys-
CC
Table
27-16). Accessing the serial programming interface
before issuing the next byte (See
WD_EEPROM
I/O
Description
I
Serial Data in
O
Serial Data out
I
Serial Clock
Table 27-17 on page
Table
before issuing the next byte (See
WD_EEPROM
before
WD_FLASH
27-16). In a
Table
2545S–AVR–07/10