IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part NumberATMEGA48V-10MU
DescriptionIC AVR MCU 4K 10MHZ 1.8V 32-QFN
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48V-10MU datasheets
 


Specifications of ATMEGA48V-10MU

Core ProcessorAVRCore Size8-Bit
Speed10MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFNPackage32MLF EP
Device CoreAVRFamily NameATmega
Maximum Speed10 MHzOperating Supply Voltage2.5|3.3|5 V
Data Bus Width8 BitNumber Of Programmable I/os23
Interface TypeSPI/TWI/USARTOn-chip Adc8-chx10-bit
Number Of Timers3Processor SeriesATMEGA48x
CoreAVR8Data Ram Size512 B
Maximum Clock Frequency10 MHzMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Minimum Operating Temperature- 40 CController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed10MHz
No. Of Timers3Rohs CompliantYes
For Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMLead Free Status / RoHS StatusLead free / RoHS Compliant
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Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
XTAL1
BS1
OE
DATA
XA0
XA1
Note:
Table 28-8.
Symbol
V
PP
I
PP
t
DVXH
t
XLXH
t
XHXL
t
XLDX
t
XLWL
t
XLPH
t
PLXH
t
BVPH
t
PHPL
t
PLBX
t
WLBX
t
PLWL
t
BVWL
t
WLWH
t
WLRL
t
WLRH
t
WLRH_CE
ATmega48/88/168
312
(1)
Timing Requirements
LOAD ADDRESS
READ DATA
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
ADDR0 (Low Byte)
DATA (Low Byte)
1. The timing requirements shown in
reading operation.
Parallel Programming Characteristics, V
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
(1)
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
READ DATA
LOAD ADDRESS
(HIGH BYTE)
t
BVDV
t
OHDZ
DATA (High Byte)
Figure 28-7
(that is, t
, t
, and t
DVXH
XHXL
= 5V ±10%
CC
Min
Typ
11.5
67
200
150
67
0
0
150
67
150
67
67
67
67
150
0
3.7
(2)
7.5
(LOW BYTE)
ADDR1 (Low Byte)
) also apply to
XLDX
Max
Units
12.5
V
μA
250
ns
μs
1
4.5
ms
9
2545S–AVR–07/10