IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part NumberATMEGA48V-10MU
DescriptionIC AVR MCU 4K 10MHZ 1.8V 32-QFN
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48V-10MU datasheets
 


Specifications of ATMEGA48V-10MU

Core ProcessorAVRCore Size8-Bit
Speed10MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFNPackage32MLF EP
Device CoreAVRFamily NameATmega
Maximum Speed10 MHzOperating Supply Voltage2.5|3.3|5 V
Data Bus Width8 BitNumber Of Programmable I/os23
Interface TypeSPI/TWI/USARTOn-chip Adc8-chx10-bit
Number Of Timers3Processor SeriesATMEGA48x
CoreAVR8Data Ram Size512 B
Maximum Clock Frequency10 MHzMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Minimum Operating Temperature- 40 CController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed10MHz
No. Of Timers3Rohs CompliantYes
For Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 257/378

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23.8.3
ADCL and ADCH – The ADC Data Register
23.8.3.1
ADLAR = 0
Bit
(0x79)
(0x78)
Read/Write
Initial Value
23.8.3.2
ADLAR = 1
Bit
(0x79)
(0x78)
Read/Write
Initial Value
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
254.
23.8.4
ADCSRB – ADC Control and Status Register B
Bit
(0x7B)
Read/Write
Initial Value
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bist
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
2545S–AVR–07/10
15
14
13
12
ADC7
ADC6
ADC5
ADC4
7
6
5
4
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
15
14
13
12
ADC9
ADC8
ADC7
ADC6
ADC1
ADC0
7
6
5
4
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
ACME
R
R/W
R
R
0
0
0
0
ATmega48/88/168
11
10
9
8
ADC9
ADC8
ADC3
ADC2
ADC1
ADC0
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
11
10
9
8
ADC5
ADC4
ADC3
ADC2
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
“ADC Conversion Result” on
3
2
1
0
ADTS2
ADTS1
ADTS0
R
R/W
R/W
R/W
0
0
0
0
ADCH
ADCL
ADCH
ADCL
ADCSRB
257