IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part NumberATMEGA48V-10MU
DescriptionIC AVR MCU 4K 10MHZ 1.8V 32-QFN
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA48V-10MU datasheets
 


Specifications of ATMEGA48V-10MU

Core ProcessorAVRCore Size8-Bit
Speed10MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size4KB (2K x 16)Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFNPackage32MLF EP
Device CoreAVRFamily NameATmega
Maximum Speed10 MHzOperating Supply Voltage2.5|3.3|5 V
Data Bus Width8 BitNumber Of Programmable I/os23
Interface TypeSPI/TWI/USARTOn-chip Adc8-chx10-bit
Number Of Timers3Processor SeriesATMEGA48x
CoreAVR8Data Ram Size512 B
Maximum Clock Frequency10 MHzMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsEWAVR, EWAVR-BL
Minimum Operating Temperature- 40 CController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size256Byte
Ram Memory Size512ByteCpu Speed10MHz
No. Of Timers3Rohs CompliantYes
For Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMLead Free Status / RoHS StatusLead free / RoHS Compliant
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Table 15-4.
Waveform Generation Mode Bit Description
WGM12
WGM11
Mode
WGM13
(CTC1)
(PWM11)
0
0
0
1
0
0
2
0
0
3
0
0
4
0
1
5
0
1
6
0
1
7
0
1
8
1
0
9
1
0
10
1
0
11
1
0
12
1
1
13
1
1
14
1
1
15
1
1
Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the
location of these bits are compatible with previous versions of the timer.
15.11.2
TCCR1B – Timer/Counter1 Control Register B
Bit
(0x81)
Read/Write
Initial Value
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
2545S–AVR–07/10
(1)
WGM10
Timer/Counter Mode of
(PWM10)
Operation
0
0
Normal
0
1
PWM, Phase Correct, 8-bit
1
0
PWM, Phase Correct, 9-bit
1
1
PWM, Phase Correct, 10-bit
0
0
CTC
0
1
Fast PWM, 8-bit
1
0
Fast PWM, 9-bit
1
1
Fast PWM, 10-bit
PWM, Phase and Frequency
0
0
Correct
PWM, Phase and Frequency
0
1
Correct
1
0
PWM, Phase Correct
1
1
PWM, Phase Correct
0
0
CTC
0
1
(Reserved)
1
0
Fast PWM
1
1
Fast PWM
7
6
5
ICNC1
ICES1
WGM13
R/W
R/W
R
R/W
0
0
0
ATmega48/88/168
Update of
x
TOP
OCR1
0xFFFF
Immediate
0x00FF
TOP
0x01FF
TOP
0x03FF
TOP
OCR1A
Immediate
0x00FF
BOTTOM
0x01FF
BOTTOM
0x03FF
BOTTOM
ICR1
BOTTOM
OCR1A
BOTTOM
ICR1
TOP
OCR1A
TOP
ICR1
Immediate
ICR1
BOTTOM
OCR1A
BOTTOM
WGM
12:0 definitions. However, the functionality and
4
3
2
1
WGM12
CS12
CS11
R/W
R/W
R/W
0
0
0
0
TOV1 Flag
at
Set on
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
0
CS10
TCCR1B
R/W
0
131