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ATMEGA48V-10MU
ATMEGA48V-10MU | |
|---|---|
| Manufacturer Part Number | ATMEGA48V-10MU |
| Description | IC AVR MCU 4K 10MHZ 1.8V 32-QFN |
| Manufacturer | Atmel |
| Series | AVR® ATmega |
| ATMEGA48V-10MU datasheets |
|
Specifications of ATMEGA48V-10MU | |||
|---|---|---|---|
| Core Processor | AVR | Core Size | 8-Bit |
| Speed | 10MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | Brown-out Detect/Reset, POR, PWM, WDT | Number Of I /o | 23 |
| Program Memory Size | 4KB (2K x 16) | Program Memory Type | FLASH |
| Eeprom Size | 256 x 8 | Ram Size | 512 x 8 |
| Voltage - Supply (vcc/vdd) | 1.8 V ~ 5.5 V | Data Converters | A/D 8x10b |
| Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN | Package | 32MLF EP |
| Device Core | AVR | Family Name | ATmega |
| Maximum Speed | 10 MHz | Operating Supply Voltage | 2.5|3.3|5 V |
| Data Bus Width | 8 Bit | Number Of Programmable I/os | 23 |
| Interface Type | SPI/TWI/USART | On-chip Adc | 8-chx10-bit |
| Number Of Timers | 3 | Processor Series | ATMEGA48x |
| Core | AVR8 | Data Ram Size | 512 B |
| Maximum Clock Frequency | 10 MHz | Maximum Operating Temperature | + 85 C |
| Mounting Style | SMD/SMT | 3rd Party Development Tools | EWAVR, EWAVR-BL |
| Minimum Operating Temperature | - 40 C | Controller Family/series | AVR MEGA |
| No. Of I/o's | 23 | Eeprom Memory Size | 256Byte |
| Ram Memory Size | 512Byte | Cpu Speed | 10MHz |
| No. Of Timers | 3 | Rohs Compliant | Yes |
| For Use With | ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to the
input capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in
Table 22-2.
ACIS1
0
0
1
1
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
22.3.3
DIDR1 – Digital Input Disable Register 1
Bit
(0x7F)
Read/Write
Initial Value
• Bit 7..2 – Res: Reserved Bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
ATmega48/88/168
242
Table
22-2.
ACIS1/ACIS0 Settings
ACIS0
Interrupt Mode
0
Comparator Interrupt on Output Toggle.
1
Reserved
0
Comparator Interrupt on Falling Output Edge.
1
Comparator Interrupt on Rising Output Edge.
7
6
5
4
–
–
–
–
R
R
R
R
0
0
0
0
3
2
1
0
–
–
AIN1D
AIN0D
R
R
R/W
R/W
0
0
0
0
2545S–AVR–07/10
DIDR1
