ATTINY84V-10MU Atmel, ATTINY84V-10MU Datasheet - Page 123

• Manufacturer Part Number: ATTINY84V-10MU
• Description: IC MCU AVR 8K FLASH 10MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.5
14.3.6
8006K–AVR–10/10
Start Condition Detector
Clock speed considerations
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
The start condition detector is shown in
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in two-wire mode.
Figure 14-6. Start Condition Detector, Logic Diagram
The start condition detector works asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,
see
of the USISIF bit on
Maximum frequency for SCL and SCK is f
receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-
trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
3. The master set the first bit to be transferred and releases the SCL line (C). The slave
4. After eight bits containing slave address and data direction (read or write) have been
5. When the slave is addressed, it holds the SDA line low during the acknowledgment
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
“Clock Sources” on page
samples the data and shifts it into the USI Data Register at the positive edge of the SCL
clock.
transferred, the slave counter overflows and the SCL line is forced low (D). If the slave
is not the one the master has addressed, it releases the SCL line and waits for a new
start condition.
cycle before holding the SCL line low again (i.e., the USI Counter Register must be set
to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave
enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
given by the master (F), or a new start condition is given.
Write( USISIF)
page 125
SDA
SCL
25) must also be taken into consideration. Refer to the description
for further details.
Figure
CK
/ 2. This is also the maximum data transmit and
14-6. The SDA line is delayed (in the range of 50
D Q
CLR
D Q
CLR
ATtiny24/44/84
USISIF
CLOCK
HOLD
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