ATTINY84V-10MU Atmel, ATTINY84V-10MU Datasheet - Page 17

• Manufacturer Part Number: ATTINY84V-10MU
• Description: IC MCU AVR 8K FLASH 10MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
8006K–AVR–10/10
EEPROM Read/Write Access
Atomic Byte Programming
Split Byte Programming
Erase
Write
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in
tion, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-
tered power supplies, V
device for some period of time to run at a voltage lower than specified as minimum for the clock
frequency used. See
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
See
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the
user must write the address into register EEAR and data into register EEDR. If the EEPMn bits
are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write
operation. Both the erase and write cycle are done in one operation and the total programming
time is given in
tions are completed. While the device is busy with programming, it is not possible to do any
other EEPROM operations.
It is possible to split the erase and write cycle in two different operations. This may be useful if
the system requires short access time for some limited period of time (typically if the power sup-
ply voltage falls). In order to take advantage of this method, it is required that the locations to be
written have been erased before the write operation. But since the erase and write operations
are split, it is possible to do the erase operations when the system allows doing time-critical
operations (typically after Power-up).
To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the
EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (program-
ming time is given in
completes. While the device is busy programming, it is not possible to do any other EEPROM
operations.
To write a location, the user must write the address into EEAR and the data into EEDR. If the
EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger
the write operation only (programming time is given in
remains set until the write operation completes. If the location to be written has not been erased
before write, the data that is stored must be considered as lost. While the device is busy with
programming, it is not possible to do any other EEPROM operations.
“Atomic Byte Programming” on page 17
Table 5-1 on page
Table 5-1 on page
“Preventing EEPROM Corruption” on page 19
CC
is likely to rise or fall slowly on Power-up/down. This causes the
22. The EEPE bit remains set until the erase and write opera-
22). The EEPE bit remains set until the erase operation
and
“Split Byte Programming” on page 17
Table 5-1 on page
Table 5-1 on page
ATtiny24/44/84
for details on how to avoid
22. A self-timing func-
22). The EEPE bit
for
17