EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 132

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

PS015313-0508
UART_TxD
Baud Rate
Transmit
Receive
IR_TxD
7-clock
Clock
delay
endec. See Universal Asynchronous Receiver/Transmitter on page 104 for more informa-
tion about the UART and its Baud Rate Generator.
The data to be transmitted via the IR transceiver is first sent to UART0. The UART trans-
mit signal (TxD) and Baud Rate Clock are used by the IrDA endec to generate the modu-
lation signal (IR_TxD) that drives the infrared transceiver. To enable transmit encoding,
the IR_RxEN bit in the IR_CTL register must be set to 0.
Each UART bit is 16-clocks wide. If the data to be transmitted is a logical 1 (High), the
IR_TxD signal remains Low (0) for the full 16-clock period. If the data to be transmitted is
a logical 0, a 3-clock High (1) pulse is output following a 7-clock Low (0) period. Follow-
ing the 3-clock High pulse, a 6-clock Low pulse completes the full 16-clock data period.
Data transmission is displayed in
function should be disabled by clearing the IR_RxEN bit in the IR_CTL reg to 0. The SIR
data format uses half-duplex communication; the UART does not transmit data while the
receiver decoder is enabled.
Data is received from the IR transceiver via the IR_RxD signal and decoded by the IrDA
endec. This decoded data is passed from the endec to UART0. To enable receiver decode,
the IR_RxEN bit in the IR_CTL register must be set to 1. The SIR data format uses half-
duplex communication; therefore, the UART should not transmit data during normal oper-
ation while the receiver decoder is enabled.
Start Bit = 0
16-clock
period
3-clock
pulse
Figure 27.Infrared Data Transmission
Data Bit 0 = 1
Figure
Data Bit 1 = 0
27. During data transmission, the IR receive
Data Bit 2 = 1
Product Specification
Infrared Encoder/Decoder
Data Bit 3 = 1
125