EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 214

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

PS015313-0508
Table 124. Flash Program Control Register; (FLASH_PGCTL= 00FFh)
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit
Position
[7:3]
[2]
ROW_PGM
[1]
PG_ERASE
[0]
MASS_ERASE
Value Description
0000
0
1
0
1
0
1
Reserved.
Row Program Disable or Row Program completed.
Row Program Enable. This bit automatically resets to 0 when
the row address reaches 128 or when the Row Program
operation times out.
Page Erase Disable (Page Erase completed).
Page Erase Enable. This bit automatically resets to 0 when the
Page Erase operation is complete.
Mass Erase Disable (Mass Erase completed).
Mass Erase Enable. This bit automatically resets to 0 when the
Mass Erase operation is complete.
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
Flash Memory
R/W
0
0
207