EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 162

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

PS015313-0508
Table 85. I
I
This register contains the data byte/slave address to be transmitted or the data byte just
received. In transmit mode, the msb of the byte is transmitted first. In receive mode, the
first bit received is placed in the msb of the register. After each byte is transmitted, the
I2C_DR register contains the byte that is present on the bus in case a lost arbitration event
occurs. See
Table 86. I
I
The I2C_CTL register is a control register that is used to control the interrupts and the
master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG
is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
When the Bus Enable bit (ENAB) is set to 0, the I
ignored and the I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
2
2
C Data Register
C Control Register
2
2
C Extended Slave Address Registers(I2C_XSAR = 00C9h)
C Data Registers(I2C_DR = 00CAh)
Table
2
C module does not respond to any address on the bus. When ENAB is
86.
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
Least-significant 8 bits of the 10-bit extended slave address.
I
7
0
7
0
2
C data byte.
2
R/W
R/W
C bus.
6
0
6
0
R/W
R/W
5
0
5
0
2
R/W
R/W
C bus inputs SCLx and SDAx are
4
0
4
0
R/W
R/W
3
0
3
0
Product Specification
R/W
R/W
2
0
2
0
I2C Serial I/O Interface
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
155