EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 158

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

PS015313-0508
Note:
Table 82. I
When all bytes are received, a NACK should be sent, then the microcontroller should
write a 1 to the STP bit in the I2C_CTL register. The I
clears the STP bit and returns to the idle state.
Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I
Read bit after a START condition. The I
bit is set to 1) and sets the IFLG bit in the I2C_CTL register and the I2C_SR register con-
tains the status code
I
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code
The data byte to be transmitted is loaded into the I2C_DR register and the IFLG bit
cleared. After the I
and the I2C_SR register contains
the I2C_DR register, the AAK bit is cleared when the IFLG is cleared. After the final byte
Code
50h
58h
38h
2
C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
2
C enters SLAVE TRANSMIT mode when it receives its own slave address and a
When I
register), it transmits an acknowledge after the first address byte is received after
a restart. An interrupt is generated, IFLG is set but the status does not change. No
second address byte is sent by the master. It is up to the slave to remember it had
been selected prior to the restart.
I
Data byte received,
ACK transmitted
Data byte received,
NACK transmitted
Arbitration lost in
NACK bit
2
2
C State
C Master Receive Status Codes For Data Bytes
2
C contains a 10-bit slave address (signified by
2
C transmits the byte and receives an acknowledge, the IFLG bit is set
A8h
.
Microcontroller Response Next I
Read DATA, clear IFLG,
clear AAK = 0
Or read DATA, clear IFLG,
set AAK = 1
Read DATA, set STA,
clear IFLG
Or read DATA, set STP,
clear IFLG
Or read DATA, set
STA & STP, clear IFLG
Same as master transmit
B8h
. When the final byte to be transmitted is loaded into
B0h
2
C then transmits an acknowledge bit (if the AAK
in the I2C_SR register.
2
C then transmits a STOP condition,
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit repeated START
Transmit STOP
Transmit STOP then
START
Same as master transmit
F0h
Product Specification
2
–
C Action
I2C Serial I/O Interface
F7h
in the I2C_SAR
151