EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 239

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

Table 148. External Read Timing
PS015313-0508
External Memory Write Timing
Figure 59
Parameter
T
T
T
T
T
T
T
T
T
T
ADDR[23:0]
1
2
3
4
5
6
7
8
9
10
DATA[7:0]
(output)
MREQ
CSx
X
WR
IN
and
Abbreviation
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Input DATA Valid to Clock Rise Setup Time
Clock Rise to DATA Hold Time
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
Clock Rise to MREQ Assertion Delay
Clock Rise to MREQ Deassertion Delay
Clock Rise to RD Assertion Delay
Clock Rise to RD Deassertion Delay
Table 149
T
7
T
1
T
Figure 59.External Memory Write Timing
5
on page 232 display the timing for external writes.
T
CLK
T
3
T
9
T
10
T
T
T
4
2
T
6
8
Product Specification
Min
Electrical Characteristics
2.0
1.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
—
Delay (ns)
Max
19.0
18.0
16.0
16.0
16.0
16.0
13
—
—
—
231