EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 246

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

Table 153. Bus Acknowledge Timing
Table 154. PHI System Clock Timing
PS015313-0508
External Bus Acknowledge Timing
External System Clock Driver (PHI) Timing
Table 153
ter detects BUSACK asserted and drives IORQN, MREQN, A[23:0] there is an asynchro-
nous prop delay to the CS[3:0] outputs being valid.
Table 154
als to synchronize with the internal system clock driver on the eZ80F92 device.
Parameter
T
T
T
Parameter
T
T
1
2
3
1
2
lists information about the bus acknowledge timing. Once the external bus mas-
lists timing information for the PHI pin. The PHI pin allows external peripher-
Abbreviation
Clock Rise to BUSACK Assertion Delay
Clock Rise to BUSACK Deassertion Delay
IORQN, MREQN, A[23:0] input to CS[3:0]
output prop delay
Abbreviation
Clock (XIN) Rise to PHI Rise
Clock (XIN) Fall to PHI Fall
Product Specification
Min
Min
Electrical Characteristics
2.0
2.0
—
—
—
Delay (ns)
Delay (ns)
Max
14.0
14.0
10.0
Max
6.0
6.0
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