EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 207

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

PS015313-0508
Flash Control Register
The Flash Control register enables or disables memory access to Flash. I/O access to the
Flash control registers and I/O programming to Flash memory are still possible while
Flash memory space access is disabled.
The minimum access time of the internal Flash is 60 ns. The Flash control register must be
configured to provide the appropriate number of WAIT states based on the system clock
frequency of the eZ80F92 device. Default on RESET is for 4 WAIT states to be inserted
for Flash memory access.
Table 116. Flash Control Register; (FLASH_CTRL= 00F8h)
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit
Position
[7:5]
FLASH_WAIT
[4]
[3]
FLASH_EN
[2:0]
Value Description
000
001
010
011
100
101
110
111
0
0
1
000
R/W
0 Wait states are inserted when Flash is active.
1 Wait state is inserted when Flash is active.
2 Wait states are inserted when Flash is active.
3 Wait states are inserted when Flash is active.
4 Wait states are inserted when Flash is active.
5 Wait states are inserted when Flash is active.
6 Wait states are inserted when Flash is active.
7 Wait states are inserted when Flash is active.
Reserved.
Flash Memory Access is disabled.
Flash Memory Access is enabled.
Reserved.
7
1
R/W
6
0
R/W
5
0
R
4
0
R/W
3
1
Product Specification
R
2
0
eZ80F92/eZ80F93
R
1
0
Flash Memory
R
0
0
200