EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 168

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

PS015313-0508
Bus Clock Speed
The I
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I
the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I
TER mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].
I
The I2C_SRR register is a Write Only register. Writing any value to this register performs
a software reset of the I
Table 91. I
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
2
2
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode).
C sampling frequency is determined by the frequency of the CPU system clock and
2
C bus at least ten times faster than the bus clock speed of the fastest master on the
2
C Software Reset Register(I2C_SRR = 00CDh)
Value
00h–FFh Writing any value to this register performs a software reset of
2
C module. See
W
X
Description
the I
7
2
C module.
W
X
6
Table
W
X
5
91.
W
X
4
W
X
3
Product Specification
W
X
2
I2C Serial I/O Interface
2
2
W
X
1
C must sam-
C in MAS-
W
X
0
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