EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 60

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

Table 14. Z80 Bus Mode Read States
PS015313-0508
STATE T1
STATE T2
STATE T3
Bus Mode Controller
eZ80 Bus Mode
Z80 Bus Mode
The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated Chip Select signal is asserted.
During State T2, the RD signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional WAIT states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered. The data is latched by the eZ80F92 device at
the rising edge of the CPU system clock at the end of State T3.
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80F92 device to be configured to connect seamlessly with external eZ80
Intel-, or Motorola-compatible devices. Bus modes for each of the chip selects can be con-
figured independently using the Chip Select Bus Mode Control Registers. The number of
CPU system clock cycles per bus mode state is also independently programmable. For
Intel
the address and the data byte both use the data bus, DATA[7:0]. Each of the bus modes is
explained in more detail in the following sections.
Chip selects configured for eZ80 bus mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown
in the
eZ80 mode.
Chip selects configured for Z80 mode modify the CPU bus signals to match the Z80
microprocessor address and data bus interface signal format and timing. During read oper-
ations, the Z80 bus mode employs three states (T1, T2, and T3) as listed in
During Write operations, Z80 bus mode employs three states (T1, T2, and T3) as listed in
Table
TM
14.
AC Characteristics
bus mode, multiplexed address and data can be selected in which the lower byte of
section on page 229. The default mode for each chip select is
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
WAIT
®
) are asserted
Table
, Z80
14.
®
-,
53