EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 251

• Manufacturer Part Number: EZ80F93AZ020SG
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F93x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3874; EZ80F93AZ020SG

Index
Numerics
100-pin LQFP package 4, 20
16-bit clock divisor value 110, 135
16-bit divisor count 110, 135
20 MHz Primary Crystal Oscillator Operation 219
32 KHz Real-Time Clock Crystal Oscillator Opera-
tion 220
A
AAK 143, 147, 148, 149, 151, 156
AAK bit 151, 152
Absolute Maximum Ratings 222
Absolute maximum ratings 222
AC Characteristics 229
ACK 143, 147, 148, 149, 150, 151, 153, 158, 159
Acknowledge 143
Address Bus 5, 6, 7, 8, 9
address bus 46, 50, 52, 53, 54, 55, 56, 57, 60, 63, 64,
67, 68, 90, 169, 179, 185
address bus, 24-bit 25
Addressing 153
ADL Memory mode 181, 185
ALARM 89, 103
alarm condition 89, 90, 102, 103
ALARM flag 102
Arbitration 145
Architectural Overview 1
asynchronous serial data 13, 15
B
Baud Rate Generator 109
Baud Rate Generator Functional Description 134
BCD—see binary-coded-decimal operation 88,
102, 103
Binary Operation 90, 91, 92, 93, 94, 95, 96, 97
binary operation 88
Binary-Coded-Decimal Operation 90, 91, 92, 93,
94, 95, 96, 97, 98, 99, 100, 101
PS015313-0508
P R E L I M I N A R Y
binary-coded-decimal operation 88
bit generation 104
Block Diagram 2
Boundary-Scan Architecture 187
break detection 104, 113
break point trigger functions 187
BRG Control Registers 110
Bus Acknowledge 12
bus acknowledge pin 52, 179
Bus Arbitration Overview 141
Bus Enable bit 155
Bus Mode Controller 53
bus mode state 53, 54, 57, 61, 65, 71
Bus Modes 66
Bus modes 53
bus modes 70
Bus Request 11
Bus Requests During ZDI Debug Mode 169
BUSACK 12, 22, 52, 169, 179, 185, 238
BUSREQ 11, 22, 52, 169, 179, 185
Byte Format 143
C
Characteristics, electrical
Chip Select 0 9
Chip Select 1 9
Chip Select 2 9
Chip Select 3 9
Chip Select Registers 67
Chip Select x Bus Mode Control Register 70
Chip Select x Control Register 69
Chip Select x Lower Bound Register 67
Chip Select x Upper Bound Register 68
Chip Select/Wait State Generator block 5, 6, 7, 8, 9
Chip Selects and Wait States 48
Chip Selects During Bus Request/Bus Acknowl-
edge Cycles 52
Clear to Send 14, 16, 122
clock divisor value, 16-bit 110, 135
clock initialization circuitry 187
Clock Peripheral Power-Down Registers 36
Clock Synchronization 144
D R A F T
Absolute maximum ratings 222
Product Specification
Index
243