HD64F3644DV Renesas Electronics America, HD64F3644DV Datasheet - Page 155

IC H8/3644 MCU FLASH 64QFP

HD64F3644DV

Manufacturer Part Number
HD64F3644DV
Description
IC H8/3644 MCU FLASH 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3644DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.7.6
Flowchart for Erasing One Block
Erase Flowcharts and Sample Programs
Address + 1
Write 0 data in all addresses to be erased
No
(set bit for block to be erased to 1)
Dummy write to verify address
(clear bit for erased block to 0)
Enable watchdog timer
Set block start address as
Clear erase block register
Select erase-verify mode
Disable watchdog timer
address
Set erase block register
(flash memory latches
(E bit = 1 in FLMCR)
Select erase mode
(read data H'FF?)
Wait (t
Wait (t
Last address?
Wait (x) ms
verify address
End of erase
Clear EV bit
Clear E bit
(prewrite)
(EV bit = 1)
Verify
address)
Start
n = 1
vs1
vs2
OK
Yes
) µs
) µs
*4
*1
*5
*6
*6
Figure 6.14 Erase Flowchart
*2
*3
NG
Erasing halts
Clear EV bit
Erase error
n
Notes: 1. Program all addresses to be erased by
N?
Yes
*6
Rev. 6.00 Sep 12, 2006 page 133 of 526
2. Set the watchdog timer overflow interval to
3. For the erase-verify dummy write, write H'FF
4. For the erase-verify operation, read the data
5. Erase time x is successively incremented to
6. t
following the prewrite flowchart.
the initial value shown in table 6.12.
using a byte transfer instruction.
using a byte transfer instruction. When
erasing multiple blocks, clear the erase block
register bits for erased blocks and perform
additional erasing only for unerased blocks.
initial set value x 2n-1 (n = 1 to 4), and is
fixed from the 4th time onward. An initial
value of 6.25 ms or less should be set, and
the time for one erasure should be 50 ms or
less.
t
N:
vs1
vs2
: 4 µs or more
: 2 µs or more
602 (set N so that the total erase time
does not exceed 30 s)
End of erase-verify
No
Double the erase time
(x
n + 1
n
2
4?
No
n
x)
REJ09B0326-0600
Section 6 ROM
Yes

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