HD64F3644DV Renesas Electronics America, HD64F3644DV Datasheet - Page 91

IC H8/3644 MCU FLASH 64QFP

HD64F3644DV

Manufacturer Part Number
HD64F3644DV
Description
IC H8/3644 MCU FLASH 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD64F3644DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3644DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bits 3 to 0 IRQ
Bit n: IRRIn
0
1
Interrupt Request Register 2 (IRR2)
Note:
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, or SCI1 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR2 is
initialized to H'00.
Bit 7 Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT
0
1
Bit 6 A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD
0
1
Bit
Initial value
Read/Write
* Only a write of 0 for flag clearing is possible.
3
IRRDT
to IRQ
R/W *
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
Setting condition:
When pin IRQ
is input
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
Setting condition:
When a direct transfer is made by executing a SLEEP instruction while DTON
= 1 in SYSCR2
Description
Clearing condition:
When IRRAD = 1, it is cleared by writing 0
Setting condition:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Description
Description
7
0
0
Interrupt Request Flags (IRRI3 to IRRI0)
IRRAD
R/W *
0
6
n
is designated for interrupt input and the designated signal edge
0
5
IRRS1
R/W *
4
0
Rev. 6.00 Sep 12, 2006 page 69 of 526
3
0
Section 3 Exception Handling
2
0
REJ09B0326-0600
1
0
(initial value)
(initial value)
(initial value)
(n = 3 to 0)
0
0

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