HD64F3644DV Renesas Electronics America, HD64F3644DV Datasheet - Page 95

• Manufacturer Part Number: HD64F3644DV
• Description: IC H8/3644 MCU FLASH 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt operation is described as follows.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
If an interrupt occurs while the interrupt enable register bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
The I bit of CCR is set to 1, masking further interrupts.
The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
Rev. 6.00 Sep 12, 2006 page 73 of 526
Section 3 Exception Handling
REJ09B0326-0600