HD64F3644DV Renesas Electronics America, HD64F3644DV Datasheet - Page 77

• Manufacturer Part Number: HD64F3644DV
• Description: IC H8/3644 MCU FLASH 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P3
high-level signal at P3
signals. In this example, the BCLR instruction is used to change pin P3
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
[B: BCLR instruction executed]
[C: After executing BCLR]
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
Input/output
Pin state
PCR3
PDR3
Input/output
Pin state
PCR3
PDR3
BCLR
#0
,
P3
Input
Low
level
0
1
P3
Output
Low
level
1
1
7
7
@PCR3
6
. The remaining pins, P3
P3
Input
High
level
0
0
P3
Output
High
level
1
0
7
6
6
and P3
6
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
The BCLR instruction is executed designating PCR3.
are input pins, with a low-level signal input at P3
5
5
5
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
to P3
4
4
0
, are output pins that output low-level
Rev. 6.00 Sep 12, 2006 page 55 of 526
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
3
3
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
0
2
2
to an input port. It is
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
REJ09B0326-0600
1
1
Section 2 CPU
7
P3
Output
Low
level
1
0
P3
Input
High
level
0
0
and a
0
0