MC9S12XDP512CAG Freescale Semiconductor, MC9S12XDP512CAG Datasheet - Page 1115

• Manufacturer Part Number: MC9S12XDP512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDP512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• For Use With: DEMO9S12XDT512E - BOARD DEMO FOR MC9S12XDT512EVB9S12XDP512E - BOARD DEMO FOR MC9S12XDP512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not
writable in normal mode. KEYACC is only writable if KEYEN (see
Register (FSEC)”
mass erase and erase verify operations. When writing to the FCNFG register in special mode, all
unimplemented/ reserved bits must be written to 0.
Freescale Semiconductor
BKSEL[1:0]
KEYACC
Reset
Reset
CBEIE
Field
CCIE
1–0
7
6
5
W
W
R
R
CBEIE
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the Flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
Block Select — The BKSEL[1:0] bits indicates which register bank is active according to
0
0
7
7
(FSTAT)”)
is set.
data.
is set to the enabled state. BKSEL is readable and writable in special mode to simplify
Figure 27-8. Flash Configuration Register (FCNFG — Normal Mode)
Figure 27-9. Flash Configuration Register (FCNFG — Special Mode)
= Unimplemented or Reserved
= Unimplemented or Reserved
is set.
CCIE
CCIE
0
0
6
6
Table 27-10. Flash Register Bank Selects
BKSEL[1:0]
Table 27-9. FCNFG Field Descriptions
KEYACC
KEYACC
MC9S12XDP512 Data Sheet, Rev. 2.21
00
01
0
0
5
5
Undefined
Undefined
0
0
4
4
Description
Selected Block
Flash Block 0
Flash Block 1
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
0
0
0
0
3
3
Section 27.3.2.6, “Flash Status Register
Section 27.3.2.6, “Flash Status Register
Section 27.3.2.2, “Flash Security
0
0
0
0
2
2
0
0
0
1
1
Table
BKSEL
27-10.
(FSTAT)”)
0
0
0
0
0
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