MC9S12XDP512CAG Freescale Semiconductor, MC9S12XDP512CAG Datasheet - Page 952

• Manufacturer Part Number: MC9S12XDP512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDP512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• For Use With: DEMO9S12XDT512E - BOARD DEMO FOR MC9S12XDT512EVB9S12XDP512E - BOARD DEMO FOR MC9S12XDP512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.57 Port J Reduced Drive Register (RDRJ)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
23.0.5.58 Port J Pull Device Enable Register (PERJ)
Read: Anytime.
Write: Anytime.
954
DDRJ[7:4]
DDRJ[2:0]
RDRJ[7:4]
RDRJ[2:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
RDRJ7
PERJ7
Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port J
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
0
1
7
7
on PTJ or PTIJ registers, when changing the DDRJ register.
= Unimplemented or Reserved
= Unimplemented or Reserved
RDRJ6
PERJ6
Figure 23-60. Port J Pull Device Enable Register (PERJ)
0
1
6
6
Figure 23-59. Port J Reduced Drive Register (RDRJ)
Table 23-52. DDRJ Field Descriptions
Table 23-53. RDRJ Field Descriptions
RDRJ5
PERJ5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
1
5
5
RDRJ4
PERJ4
0
1
4
4
Description
Description
0
0
0
0
3
3
RDRJ2
PERJ2
0
1
2
2
RDRJ1
Freescale Semiconductor
PERJ1
0
1
1
1
RDRJ0
PERJ0
0
1
0
0