HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 205

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
Bit
5
4
3
2
1
0
*
Bit
Name
DMAIWA 0
ENDIAN 0/1 *
HIZMEM 0
HIZCNT 0
The external pin for specifying endian (MD5) is sampled on power-on reset.
When big endian is specified, this bit is read as 0 and when little endian is specified,
this bit is read as 1.
Initial
Value
1
0
R/W
R/W
R
R
R
R/W
R/W
Description
Method of inserting wait states between access cycles when
DMA single address transfer is performed.
Specifies the method of inserting the idle cycles specified by
the DMAIW1 and DMAIW0 bits. Clearing this bit will make this
LSI insert the idle cycles when another device, which includes
this LSI, drives the data bus after an external device with
DACK drove it. Setting this bit will make this LSI insert the idle
cycles even when the continuous accesses to an external
device with DACK are performed.
Reserved
This bit is always read as 1. The write value should always be
1.
Endian Flag
Samples the external pin for specifying endian on power-on
reset (MD5). All address spaces are defined by this bit. This is
a read-only bit.
0: The external pin for specifying endian (MD5) was low level
1: The external pin for specifying endian (MD5) was high level
Reserved
This bit is always read as 0. The write value should always be
0.
High-Z Memory Control
Specifies the pin state in software standby mode for A25 to
A0,
0: High impedance in software standby mode.
1: Driven in software standby mode
High-Z Control
Specifies the state in software standby mode and bus
released for
0: High impedance in software standby mode and bus
1: Driven in standby mode and bus released for
on power-on reset. This LSI is being operated as big
endian.
on power-on reset. This LSI is being operated as little
endian.
released for
R A S L
B S
,
C S
,
C A S U
, RD/
R A S U
R A S U
, and
W R
,
R A S L
,
,
W E
C A S L
R A S L
, and
,
C A S U
.
Rev. 2.00, 09/03, page 157 of 690
,
C A S U
R D
, and
.
, and
C A S L
C A S L
.
.
R A S U
,