HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 251

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex
A2/3 BSZ[1:0]
11 (32 bits)
Output Pin of
This LSI
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Example of connected memory
256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9 bits product): 1 device
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 2 devices
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
2. Bank address specification
access mode.
Output (2)-1
A2/3 ROW[1:0]
01 (12 bits)
Row Address
Output Cycle
A26
A25
A24 *
A23 *
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
2
2
Setting
A2/3 COL[1:0]
01 (9 bits)
Column Address
Output Cycle
A17
A16
A24 *
A23 *
A13
L/H *
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
2
Synchronous DRAM
Pin
A13 (BA1)
A12 (BA0)
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Rev. 2.00, 09/03, page 203 of 690
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Unused