HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 569

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.11.2 Port L Data Register (PLDR)
PLDR is an 8-bit read-only register that stores data for pins PTL3 to PTL0. Bits PL3DT to PL0DT
correspond to pins PTL3 to PTL0. If the port is read, the corresponding pin level is read.
Table 20.11 Port L Data Register (PLDR) Read/Write Operation
Note: n = 0 to 3
20.12
Port M is a 6-bit input/output port with the pin configuration shown in figure 20.12. Each pin has
an input pull-up MOS, which is controlled by the port M control register (PMCR) in the PFC.
PLnMD1 PLnMD0 Pin State
0
1
Bit
7 to 4
3 to 0
PLCR State
Port M
Bit
Name
—
PL3DT
to
PL0DT
0
1
0
1
Initial
Value
0
0
Other function Read as 0
Setting
prohibited
Setting
prohibited
Input (Pull-up
MOS off)
Port M
R/W
R
R
Figure 20.12 Port M
Read
—
—
Pin state
Description
Reserved
These bits are always read as 0.
Table 20.11 shows the function of PLDR.
PTM6 (input/output)/VBUS (input)
PTM4 (input)/NF (input)
PTM3 (input/output)
PTM2 (input/output)
PTM1 (input/output)
PTM0 (input/output)
Write
Invalid (no effect on pin state)
—
—
Invalid (no effect on pin state)
Rev. 2.00, 09/03, page 521 of 690