HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 476

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.6
Notes on Usage
Note the following when using the SCIF.
a. SCFTDR Writing and the TDFE Flag:
The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes
written in the transmit FIFO data register (SCFTDR) has fallen to or below the transmit trigger
number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set,
transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient
continuous transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE
clearing should therefore be carried out when SCFTDR contains more than the transmit trigger
number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the 14 to 8 bits of the FIFO data
count register (SCFDR).
b. SCFRDR Reading and the RDF Flag:
The RDF flag in the serial status register (SCSSR) is set when the number of receive data bytes in
the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger
number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set,
receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient
continuous reception.
However, if the number of data bytes in SCFRDR is still equal to or greater than the trigger
number after a read, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore
be cleared to 0 after being read as 1 after all receive data has been read.
The number of receive data bytes in SCFRDR can be found from the 6 to 0 bits of the FIFO data
count register (SCFDR).
c. Break Detection and Processing:
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set.
Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive
operation continues.
Rev. 2.00, 09/03, page 428 of 690