HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 294

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6
5
4
3
2
Rev. 2.00, 09/03, page 246 of 690
Bit
Name
DL
DS
TB
TS1
TS0
IE
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
DREQ Level and DREQ Edge Select
Select the detection method of the DREQ pin input and the
detection level.
These bits are valid only in CHCR_0 and CHCR_1. These bits
are always read as 0 in CHCR_2 and CHCR_3. The write value
should always be 0.
In channels 0 and 1, also, if the transfer request source is
specified as an on-chip peripheral module or if an auto-request
is specified, these bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
Transfer Size
Specify the size of data to be transferred.
Select the size of data to be transferred when the source or
destination is an on-chip peripheral module register of which
transfer size is specified.
00: Byte size
01: Word size (two bytes)
10: Longword size (four bytes)
11: 16-byte unit (four longword transfers)
Interrupt Enable
Specifies whether or not an interrupt request is generated to the
CPU at the end of the DMA transfer. Setting this bit to 1
generates an interrupt request (DEI) to the CPU when the TE
bit is set to 1.
0: Interrupt request disabled
1: Interrupt request enabled