HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 297

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
2
1
0
Note: * Only 0 can be written for clearing the flags.
Bit
Name
AE
NMIF
DME
Initial
Value
0
0
0
R/W
R/(W) * Address Error Flag
R/(W) * NMI Flag
R/W
Description
Indicates that an address error occurred by the DMAC. If this
bit is set, DMA transfer is not enabled even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1. This bit can
only be cleared by writing 0 after reading 1.
0: No DMAC address error
[Clearing conditions]
1: DMAC address error. DMA transfer disabled.
[Setting condition]
DMAC address error occurrence
Indicates that an NMI interrupt occurred. If this bit is set, DMA
transfer is not enabled even if the DE bit in CHCR and the
DME bit in DMAOR are set to 1. This bit can only be cleared
by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can be
done in one transfer unit. When the DMAC is not in operation,
the NMIF bit is set to 1 even if the NMI interrupt was input.
0: No NMI interrupt
[Clearing conditions]
1: NMI input. DMA transfer disabled.
[Setting condition]
NMI interrupt occurrence
DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, DMA transfers
are enabled. In this time, all of the bits TE in CHCR, NMIF in
DMAOR, and AE must be 0. If this bit is cleared during
transfer, transfers in all the channels can be terminated.
0: Disable DMA transfers on all channels
1: Enable DMA transfers on all channels
Writing 0 after reading AE = 1
Power-on reset
Manual reset
Writing 0 after reading NMIF = 1
Power-on reset
Manual reset
Rev. 2.00, 09/03, page 249 of 690