HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 42

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read 4)
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Single Read 4)
Figure 25.33 Synchronous DRAM Burst Write Bus Cycle (Single Write 4)
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Single Write 4)
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Single Write 4)
Figure 25.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle) ............................. 660
Figure 25.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle) .............................. 661
Figure 25.38 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle).................. 662
Figure 25.39 Access Timing in Low-Frequency Mode (Auto Precharge) ................................ 664
Figure 25.40 Synchronous DRAM Auto-Refresh Timing
Figure 25.41 Synchronous DRAM Self-Refresh Timing
Figure 25.42 Synchronous DRAM Mode Register Write Timing
Figure 25.43 DREQ Input Timing ......................................................................................... 668
Figure 25.44 DACK, TEND Output Timing .......................................................................... 668
Figure 25.45 TCLK Input Timing.......................................................................................... 669
Figure 25.46 TCLK Clock Input Timing................................................................................ 669
Figure 25.47 Oscillation Settling Time when RTC Crystal Oscillator Is Turned On ................ 670
Figure 25.48 TPU Output Timing .......................................................................................... 670
Figure 25.49 SCK Input Clock Timing .................................................................................. 671
Figure 25.50 SCIF Input/Output Timing in Clock Synchronous Mode.................................... 672
Figure 25.51 USB Clock Timing ........................................................................................... 672
Figure 25.52 Oscillation Settling Time when USB Crystal Oscillator Is Turned On ................ 673
Figure 25.53 I/O Port Timing ................................................................................................ 674
Figure 25.54 TCK Input Timing ............................................................................................ 675
Figure 25.55
Figure 25.56 UDI Data Transfer Timing ................................................................................ 676
Figure 25.57
Figure 25.58 Output Load Circuit .......................................................................................... 677
Rev. 2.00, 09/03, page xl of xlvi
(Bank Active Mode: READ Command, Same Row Address,
(Bank Active Mode: PRE + ACTV + READ Commands,
(Bank Active Mode: ACTV + WRITE Commands, TRCD = 1 Cycle,
(Bank Active Mode: WRITE Command, Same Row Address,
(Bank Active Mode: PRE + ACTV + WRITE Commands,
(TRP = 2 Cycle, Low-Frequency Mode) ............................................................ 665
(TRP = 2 Cycle, Low-Frequency Mode) ............................................................ 666
(TRP = 2 Cycle, Low-Frequency Mode) ............................................................ 667
T R S T
A S E M D 0
CAS Latency = 2, TRCD = 1 Cycle) ................................................................. 655
Different Row Address, CAS Latency = 2, TRCD = 1 Cycle)............................ 656
TRWL = 1 Cycle)............................................................................................. 657
TRCD = 1 Cycle, TRWL = 1 Cycle) ................................................................. 658
Different Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle)............................ 659
Input Timing (Reset Hold) ...................................................................... 676
Input Timing..................................................................................... 676