HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 184
HD6417750RF200DV
Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF200DV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
HD6417750RF200DV
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FREESCALE
Quantity:
450
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Section 3 Memory Management Unit (MMU)
3.6.3
An instruction TLB protection violation exception occurs when, even though an ITLB entry
contains address translation information matching the virtual address to which an instruction
access is made, the actual access type is not permitted by the access right specified by the PR bit.
The instruction TLB protection violation exception processing carried out by hardware and
software is shown below.
Hardware Processing: In the event of an instruction TLB protection violation exception,
hardware carries out the following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'0A0 in EXPEVT.
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
Software Processing (Instruction TLB Protection Violation Exception Handling Routine):
Resolve the instruction TLB protection violation, execute the exception handling return instruction
(RTE), terminate the exception handling routine, and return control to the normal flow. The RTE
instruction should be issued at least one instruction after the LDTLB instruction.
3.6.4
A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual
address to which a data access has been made. A data TLB multiple hit exception is also generated
if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.
When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not
guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted.
Rev.7.00 Oct. 10, 2008 Page 98 of 1074
REJ09B0366-0700
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
saved in SGR.
starts the instruction TLB protection violation exception handling routine.
Instruction TLB Protection Violation Exception
Data TLB Multiple Hit Exception
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